EP2AGX95EF29C6N Datasheet, PDF (113/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 5: Clock Networks and PLLs in Arria II Devices
5–5
Clock Networks in Arria II Devices
Figure 5–3. RCLK Networks in Arria II GX Devices
Top Left PLL
PLL_1
CLK[12..15]
RCLK[42..47]
RCLK[36..41]
Top Right PLL
PLL_2
RCLK[0..5] (2)
RCLK[30..35]
RCLK[6..11] (2)
Q1 Q2
Q4 Q3
RCLK[12..17] RCLK[18..23]
PLL_5 (1) _{Center PLLs}
PLL_6 ^{(1) CLK[8..11]}
RCLK[24..29]
PLL_4
PLL_3
Bottom Left PLL
CLK[4..7]
Bottom Right PLL
Notes to Figure 5–3:
(1) PLL_5 and PLL_6 are only available in EP2AGX95, EP2AGX125, EP2AGX190, and EP2AGX260 devices.
(2) RCLK[0..5] is not driven by any clock pins because there are no dedicated clock pins on the left side of the Arria II GX devices.
Figure 5–4. RCLK Networks in Arria II GZ Devices (Note 1)
CLK[12..15]
T1 T2
RCLK[54..63] RCLK[44..53]
L2
CLK[0..3]
L3
RCLK[0..5]
RCLK[6..11]
Q1 Q2
Q4 Q3
RCLK[38..43]
RCLK[32..37]
R2 _CLK[8..11]
R3
RCLK[12..21] RCLK[22..31]
B1 B2
CLK[4..7]
Note to Figure 5–4:
(1) A maximum of four signals from the core can drive into each group of RCLKs. For example, only four core signals can drive into RCLK[0..5] and
another four core signals can drive into RCLK[54..63] at any one time.
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration