EP2AGX95EF29C6N Datasheet, PDF (331/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
Device Configuration Pins
9–45
Table 9–18 lists the dedicated JTAG pins. JTAG pins must be kept stable before and
during configuration to prevent accidental loading of JTAG instructions. The TDI, TMS,
and TRST pins have weak internal pull-up resistors; the TCK pin has a weak internal
pull-down resistor (typically 25 k ). If you plan to use the SignalTap embedded
logic array analyzer, you must connect the JTAG pins of the Arria II device to a JTAG
header on your board.
Table 9–18. Dedicated JTAG Pins
Pin Name User Mode Pin Type
Description
Serial input pin for instructions as well as test and programming data. Data is
shifted on the rising edge of TCK. The TDI pin is powered by the V_CCIO power
TDI
N/A
Test data ^{supply for Arria II GX devices and the V}CCPD ^{power supply for Arria II GZ}
input ^devices.
If the JTAG interface is not required on your board, you can disable the JTAG
circuitry by connecting this pin to logic high.
Serial data output pin for instructions as well as test and programming data.
Data is shifted out on the falling edge of TCK. The pin is tri-stated if data is not
being shifted out of the device. The TDO pin is powered up by the V_CCPD/V_CCIO
TDO
N/A
Test data ^{power supply. For more information about connecting a JTAG chain with}
output ^{multiple voltages across the devices in the chain, refer to the JTAG}
Boundary-Scan Testing in Arria II Devices chapter.
If the JTAG interface is not required on your board, you can disable the JTAG
circuitry by leaving this pin unconnected.
Input pin that provides the control signal to determine the transitions of the
TAP controller state machine. TMS is evaluated on the rising edge of TCK.
Therefore, you must set up TMS before the rising edge of TCK. Transitions in the
TMS
N/A
Test mode _{state machine occur on the falling edge of TCK after the signal is applied to TMS.}
select
The TMS pin is powered by the V_CCPD/V_CCIO power supply.
If the JTAG interface is not required on your board, you can disable the JTAG
circuitry by connecting this pin to logic high.
Clock input to the BST circuitry. Some operations occur at the rising edge while
others occur at the falling edge. The TCK pin is powered by the V_CCPD/V_CCIO
TCK
N/A
Test clock ^{power supply.}
input It is expected that the clock input waveform have a nominal 50% duty cycle.
If the JTAG interface is not required on your board, you can disable the JTAG
circuitry by connecting TCK to GND.
TRST (1)
Active-low input to asynchronously reset the boundary-scan circuit. The TRST
pin is optional according to the IEEE Std. 1149.1 standard. The TRST pin is
Test reset ^{powered by the VCCPD power supply for Arria II GZ devices.}
N/A
input Hold TMS at one or keep TCK static while TRST is changed from 0 to 1.
(optional) _{If the JTAG interface is not required on your board, you can disable the JTAG}
circuitry by connecting the TRST pin to GND. You need one k pull-up resistor
to V_CCPD if you do not use the TRST pin.
Note to Table 9–18:
(1) The TRST pin is only available for Arria II GZ devices.
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration