EP2AGX95EF29C6N Datasheet, PDF (226/380 Pages) Altera Corporation – Device Interfaces and Integration

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Chapter 7: External Memory Interfaces in Arria II Devices
Arria II External Memory Interface Features
Arria II External Memory Interface Features
Arria II devices are rich with features that allow robust high-performance external
memory interfacing. The Altera^® Memory IPs allow you to use these external memory
interface features and helps set up the physical interface (PHY) best suited for your
system. This section describes each Arria II devices feature that is used in external
memory interfaces from the DQS phase-shift circuitry, dynamic OCT control block,
and DQS logic block.
1 If you use the Altera memory controller MegaCore^® functions, the ALTMEMPHY
megafunction and UniPHY IP core are instantiated for you.
f For more information about supported external memory IPs, refer to
Section III: External Memory Interface System Specification in volume 1 of the External
Memory Handbook.
DQS Phase-Shift Circuitry
Arria II phase-shift circuitry provides phase shift to the DQS/CQ and CQn pins on
read transactions when the DQS/CQ and CQn pins are acting as input clocks or
strobes to the FPGA. DQS phase-shift circuitry consists of DLLs that are shared
between the multiple DQS pins and the phase-offset control module to further
fine-tune the DQS phase shift for different sides of the device.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
June 2011 Altera Corporation