EP2AGX95EF29C6N Datasheet, PDF (257/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
Differential Receiver
8–11
You can statically assign the V_OD settings from the Assignment Editor. Table 8–6 lists
the assignment name for programmable V_OD and its possible values in the Quartus II
software Assignment Editor.
Table 8–6. Programmable V_OD Settings in Quartus II Software Assignment Editor
Assignment Name
Assignment Value
Arria II GX Device
Arria II GZ Device
Programmable Differential Output
Voltage (V_OD)
2
0, 1, 2, 3
Differential Receiver
The Arria II device family has a dedicated circuitry to receive high-speed differential
signals in side or row I/Os. Figure 8–8 shows the hardware blocks of the Arria II
receiver. The receiver has a differential buffer and PLLs that can be shared between
the transmitter and receiver, a DPA block, a synchronizer, a data realignment block,
and a deserializer. The differential buffer can receive LVDS signal levels, which are
statically set in the Quartus II software Assignment Editor. Figure 8–8 shows a block
diagram of an LVDS receiver in the right I/O bank.
Figure 8–8. LVDS Receiver Block Diagram (Note 1), (2)
rx_out
10
IOE Supports SDR, DDR, or Non-Registered Datapath
2
IOE
FPGA
Fabric
rx_divfwdclk
rx_outclock
Deserializer
DOUT DIN
Bit Slip
DOUT DIN
2
(LOAD_EN, diffioclk)
diffioclk
Clock
Multiplexer
LVDS Receiver
+
rx_in
Synchronizer
DOUT DIN
DPA Circuitry
Retimed
Data ^DIN
DPA Clock
3
(DPA_LOAD_EN,
DPA_diffioclk,
rx_divfwdclk)
3
(LVDS_LOAD_EN,
LVDS_diffioclk,
rx_outclk)
PLL (3)
rx_inclock
Notes to Figure 8–8:
(1) In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively.
(2) The rx_out port has a maximum data width of 10 bits.
(3) Arria II GX center/corner PLL or Arria II GZ left/right PLL.
8 Serial LVDS
Clock Phases
LVDS Clock Domain
DPA Clock Domain
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration