EP2AGX95EF29C6N Datasheet, PDF (165/380 Pages) Altera Corporation – Device Interfaces and Integration

December 2011
AIIGX51006-4.2
AIIGX51006-4.2
6. I/O Features in Arria II Devices
This chapter describes how Arria^® II devices provide I/O capabilities that allow you
to work in compliance with current and emerging I/O standards and requirements.
With these device features, you can reduce board design interface costs and increase
development flexibility.
Package and die enhancements with dynamic termination and output control provide
best-in-class signal integrity. Numerous I/O features assist high-speed data transfer
into and out of the device, including:
■ Single-ended, non-voltage-referenced, and voltage-referenced I/O standards
■ Low-voltage differential signaling (LVDS), reduced swing differential signal
(RSDS), mini-LVDS, high-speed transceiver logic (HSTL), and SSTL
■ Bus LVDS (BLVDS) for Arria II GX devices
■ Programmable output current strength
■ Programmable slew rate
■ Programmable bus-hold
■ Programmable pull-up resistor
■ Open-drain output
■ On-chip series termination (R_S OCT)
■ On-chip differential termination (R_D OCT)
■ On-chip parallel termination (R_T OCT) for Arria II GZ devices
■ Dynamic OCT for Arria II GZ devices
■ Programmable pre-emphasis
■ Programmable voltage output differential (V_OD)
This chapter includes the following sections:
■ “I/O Standards Support” on page 6–2
■ “I/O Banks” on page 6–5
■ “I/O Structure” on page 6–10
■ “OCT Support” on page 6–19
■ “Arria II OCT Calibration” on page 6–26
■ “Termination Schemes for I/O Standards” on page 6–28
■ “I/O Bank Restrictions” on page 6–36
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Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2011
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