EP2AGX95EF29C6N Datasheet, PDF (223/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 7: External Memory Interfaces in Arria II Devices
Combining ×16/×18 DQ/DQS Groups for ×36 QDR II+/QDR II SRAM Interface
7–21
Using the R_UP and R_DN Pins in a DQ/DQS Group Used for Memory Interfaces
in Arria II GZ Devices
You can use the DQS/DQSn pins in some of the ×4 groups as R_UP and R_DN pins (listed
in the pin table). You cannot use a ×4 DQ/DQS group for memory interfaces if any of
its pin members are used as R_UP and R_DN pins for OCT calibration. You may be able to
use the ×8/×9 group that includes this ×4 DQ/DQS group, if either of the following
applies:
■ You are not using DM pins with your differential DQS pins
■ You are not using complementary or differential DQS pins
You can use the ×8/×9 group because a DQ/DQS ×8/×9 group actually comprises 12
pins, because the groups are formed by stitching two DQ/DQS groups in ×4 mode
with six pins each (refer to Table 7–1 on page 7–5). A typical ×8 memory interface
consists of one DQS, one DM, and eight DQ pins that add up to 10 pins. If you choose
your pin assignment carefully, you can use the two extra pins for R_UP and R_DN. In a
DDR3 SDRAM interface, you must use differential DQS, which means that you only
have one extra pin. In this case, pick different pin locations for the R_UP and R_DN pins
(for example, in the bank that contains the address and command pins).
You cannot use the R_UP and R_DN pins shared with DQ/DQS group pins when using
×9 QDR II+/QDR II SRAM devices, because the R_UP and R_DN pins are dual purpose
with the CQn pins. In this case, pick different pin locations for R_UP and R_DN pins to
avoid conflict with memory interface pin placement. You have the choice of placing
the R_UP and R_DN pins in the data-write group or in the same bank as the address and
command pins.
There is no restriction on using ×16/×18 or ×32/×36 DQ/DQS groups that include the
×4 groups whose pins are being used as R_UP and R_DN pins, because there are enough
extra pins that can be used as DQS pins.
1 For ×8, ×16/×18, or ×32/×36 DQ/DQS groups whose members are used for R_UP and
R_DN, you must assign DQS and DQ pins manually. The Quartus^® II software might
not be able to place DQS and DQ pins without manual pin assignments, resulting in a
“no-fit”.
Combining ×16/×18 DQ/DQS Groups for ×36 QDR II+/QDR II SRAM
Interface
This implementation combines ×16/×18 DQ/DQS groups to interface with a ×36
QDR II+/QDR II SRAM device. The ×36 read data bus uses two ×16/×18 groups, and
the ×36 write data uses another two ×16/×18 or four ×8/×9 groups. The CQ/CQn
signal traces are split on the board trace to connect to two pairs of CQ/CQn pins in
the FPGA. This is the only connection on the board that you must change for this
implementation. Other QDR II+/QDR II SRAM interface rules for Arria II devices
also apply for this implementation.
1 The ALTMEMPHY megafunction and UniPHY IP core do not use the QVLD signal, so
you can leave the QVLD signal unconnected as in any QDR II+/QDR II SRAM
interfaces in Arria II devices.
June 2011 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration