EP2AGX95EF29C6N Datasheet, PDF (228/380 Pages) Altera Corporation – Device Interfaces and Integration

7–26
Chapter 7: External Memory Interfaces in Arria II Devices
Arria II External Memory Interface Features
Figure 7–19. DQS/CQ and CQn Pins and DQS Phase-Shift Circuitry for Arria II GZ Devices (Note 1)
DLL
Reference
Clock (2)
DQS/CQ CQn
Pin
Pin
Δt
Δt
DQS/CQ
Pin
DQS Logic
Blocks
Δt
CQn
Pin
Δt
DLL
Reference
Clock (2)
DQS
Phase-Shift
Circuitry
to IOE to IOE
to IOE
DQS
Phase-Shift
to IOE ^Circuitry
to
IOE
DQS/CQ
Pin
Δt
to
IOE
to
IOE
CQn
Pin
Δt
to
IOE
DQS Logic
Blocks
Δt
Δt
CQn
Pin
DQS/CQ
Pin
DQS/CQ
Pin
Δt
to
IOE
CQn
Pin
Δt
to
IOE
to
Δt
CQn
IOE
Pin
to
Δt
DQS/CQ
IOE
Pin
DQS
to IOE
Phase-Shift
Circuitry
to IOE
Δt
Δt
to IOE to IOE
Δt
Δt
DQS
Phase-Shift
Circuitry
DLL
Reference
Clock (2)
CQn
Pin
DQS/CQ
Pin
CQn DQS/CQ
Pin
Pin
DLL
Reference
Clock (2)
Notes to Figure 7–19:
(1) For possible reference input clock pins for each DLL, refer to “DLL” on page 7–27.
(2) You can configure each DQS/CQ and CQn pin with a phase shift based on one of two possible DLL output settings.
DQS phase-shift circuitry is connected to DQS logic blocks that control each DQS/CQ
or CQn pin. The DQS logic blocks allow the DQS delay settings to be updated
concurrently at every DQS/CQ or CQn pin.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
June 2011 Altera Corporation