EP2AGX95EF29C6N Datasheet, PDF (263/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
Differential Receiver
8–17
Figure 8–13. Receiver Datapath in Non-DPA Mode (Note 1), (2), (3)
10
rx_out
IOE Supports SDR, DDR, or Non-Registered Datapath
2
IOE
FPGA
Fabric
rx_divfwdclk
rx_outclock
Deserializer
DOUT DIN
Bit Slip
DOUT DIN
2
(LOAD_EN, diffioclk)
diffioclk
Clock
Multiplexer
LVDS Receiver
+
rx_in
Synchronizer
DOUT DIN
DPA Circuitry
Retimed _DIN
Data
DPA Clock
3 _{(DPA_LOAD_EN,}
DPA_diffioclk,
rx_divfwdclk)
3 ^{(LVDS_LOAD_EN,}
LVDS_diffioclk,
rx_outclk)
PLL (4)
rx_inclock
8 Serial LVDS
Clock Phases
Notes to Figure 8–13:
(1) All disabled blocks and signals are grayed out.
(2) In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively.
(3) The rx_out port has a maximum data width of 10 bits.
(4) Arria II GX center/corner PLL or Arria II GZ left/right PLL.
LVDS Clock Domain
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration