EP2AGX95EF29C6N Datasheet, PDF (374/380 Pages) Altera Corporation – Device Interfaces and Integration

11–8
Chapter 11: JTAG Boundary-Scan Testing in Arria II Devices
Document Revision History
Document Revision History
Table 11–6 lists the revision history for this document.
Table 11–6. Document Revision History
Date
December 2013
December 2010
July 2010
November 2009
February 2009
Version
Changes
4.1 Updated the “EXTEST_PULSE Instruction Mode” section.
■ Updated for the Quartus II software version 10.1 release.
■ Added Arria II GZ devices information.
■ Added “BST Architecture for Arria II Devices” and “Disabling IEEE Std. 1149.1 BST
4.0
Circuitry” sections.
■ Added Table 11–3 and Table 11–5.
■ Updated Table 11–1 and Table 11–2.
■ Minor text edits.
Updated for Arria II GX v10.0 release:
3.0 ■ Updated “BST Operation Control” section.
■ Minor text edits.
Updated for Arria II GX v9.1 release:
■ Updated Table 11–1 and Table 11–2.
2.0
■ Updated “I/O Voltage Support in a JTAG Chain” section.
■ Minor text edits.
1.0 Initial release.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2013 Altera Corporation