EP2AGX95EF29C6N Datasheet, PDF (34/380 Pages) Altera Corporation – Device Interfaces and Integration

2–4
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II Devices
Logic Array Blocks
LAB Control Signals
Each LAB contains dedicated logic for driving a maximum of 10 control signals to its
ALMs at a time. Control signals include three clocks, three clock enables, two
asynchronous clears, a synchronous clear, and synchronous load control signals.
Although you generally use synchronous-load and clear signals when implementing
counters, you can also use them with other functions. Each LAB has two unique clock
sources and three clock enable signals, as shown in Figure 2–4. The LAB control block
can generate up to three clocks using two clock sources and three clock enable signals.
Each clock and clock enable signals are linked. For example, any ALM in a particular
LAB using the labclk1 signal also uses the labclkena1 signal. If the LAB uses both
the rising and falling edges of a clock, it also uses two LAB-wide clock signals.
De-asserting the clock enable signal turns off the corresponding LAB-wide clock. The
LAB row clocks [5..0] and LAB local interconnects generate the LAB-wide control
signals. In addition to data, the inherent low skew of the MultiTrack interconnect
allows clock and control signal distribution.
Figure 2–4. LAB-Wide Control Signals
6
Dedicated Row LAB Clocks
6
There are two unique
clock signals per LAB.
6
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
labclk0
labclk1
labclk2
syncload
labclkena0
or asyncload
or labpreset
labclkena1
labclkena2
labclr0
labclr1
synclr
Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2010 Altera Corporation