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EP2AGX95EF29C6N Datasheet, PDF (300/380 Pages) Altera Corporation – Device Interfaces and Integration
9–14
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
Fast Passive Parallel Configuration
If a system has multiple devices that contain the same configuration data, tie all
device nCE inputs to GND and leave the nCEO pins floating. All other configuration
pins (nCONFIG, nSTATUS, DCLK, DATA[7..0], and CONF_DONE) are connected to every
device in the chain. Configuration signals may require buffering to ensure signal
integrity and prevent clock skew problems. Ensure that the DCLK and DATA lines are
buffered for every fourth device. Devices must be the same density and package. All
devices start and complete configuration at the same time.
Figure 9–3 shows a multi-device FPP configuration when both Arria II devices are
receiving the same configuration data.
Figure 9–3. Multiple-Device FPP Configuration Using an External Host When Both Devices Receive the Same Data
Memory
ADDR DATA[7..0]
(1) (1) (2)
10 kΩ
10 kΩ 10 kΩ
External Host
(MAX II Device or
Microprocessor)
Arria II Device 1
MSEL[n..0]
(3)
CONF_DONE
nSTATUS
nCE
nCEO
N.C.
GND
DATA[7..0]
nCONFIG
DCLK
Arria II Device 2
MSEL[n..0]
(3)
CONF_DONE
nSTATUS
nCE
nCEO
N.C.
GND
DATA[7..0]
nCONFIG
DCLK
Notes to Figure 9–3:
(1) Connect the pull-up resistor to a supply that provides an acceptable input signal for the Arria II device. For Arria II GX devices, use the VCCIO pin.
For Arria II GZ devices, use the VCCPGM pin. VCCIO/VCCPGM must be high enough to meet the VIH specification of the I/O on both the device and the
external host. Altera recommends powering up the configuration system I/Os with VCCIO/VCCPGM.
(2) A pull-up resistor to VCCIO/VCCPGM or a pull-down resistor keeps the nCONFIG line in a known state when the external host is not driving the line.
(3) The MSEL pin settings vary for different configuration voltage standards and POR delay. To connect MSEL[3..0]for an Arria II GX device, refer to
Table 9–6 on page 9–9. To connect MSEL[2..0] for an Arria II GZ device, refer to Table 9–7 on page 9–10.
You can use a single configuration chain to configure Arria II devices with other
Altera devices that support FPP configuration. To ensure that all devices in the chain
complete configuration at the same time, or that an error flagged by one device
initiates reconfiguration in all devices, tie all of the device CONF_DONE and nSTATUS
pins together.
f For more information about configuring multiple Altera devices in the same
configuration chain, refer to the Configuring Mixed Altera FPGA Chains chapter in
volume 2 of the Configuration Handbook.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation