EP2AGX95EF29C6N Datasheet, PDF (253/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
8–7
LVDS SERDES and DPA Block Diagram
LVDS SERDES and DPA Block Diagram
The Arria II GX devices have dedicated SERDES and DPA circuitry for LVDS
transmitters and receivers on the right side. The Arria II GZ devices have dedicated
SERDES and DPA circuitry for LVDS transmitters and receivers on the row I/O banks.
Figure 8–3 shows the LVDS SERDES and DPA block diagram. This diagram shows the
interface signals for the transmitter and receiver datapaths. For more information,
refer to “Differential Transmitter” on page 8–8 and “Differential Receiver” on
page 8–11.
Figure 8–3. LVDS SERDES and DPA Block Diagram (Note 1), (2), (3)
tx_in ₁₀
Serializer ₂
IOE
DIN DOUT
IOE Supports SDR, DDR, or
Non-Registered Datapath
tx_out
+
-
tx_coreclock
rx_out ¹⁰
FPGA
Fabric
3 ^{(LVDS_LOAD_EN, diffioclk,}
tx_coreclock)
IOE Supports SDR, DDR, or
Non-Registered Datapath
2
IOE
Deserializer
DOUT DIN
Bit Slip
DOUT DIN
LVDS Transmitter
Synchronizer
DOUT DIN
DPA Circuitry
Retimed
Data
DIN
DPA Clock
rx_in
+
-
rx_divfwdclk
rx_outclock
diffioclk
2
(LOAD_EN, diffioclk)
Clock Multiplexer
3
(DPA_LOAD_EN,
DPA_diffioclk,
rx_divfwdclk)
LVDS Receiver
3 _{(LVDS_LOAD_EN,}
LVDS_diffioclk,
rx_outclock
PLL (4)
8 Serial LVDS
Clock Phases
LVDS Clock Domain
DPA Clock Domain
rx_inclock/tx_inclock
Notes to Figure 8–3:
(1) This diagram shows a shared PLL between the transmitter and receiver. If the transmitter and receiver are not sharing the same PLL, two PLLs
on the right side of the device are required.
(2) In SDR and DDR modes, the data width is 1 and 2 bits, respectively.
(3) The tx_in and rx_out ports have a maximum data width of 10 bits.
(4) Arria II GX center/corner PLL or Arria II GZ left/right PLL.
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration