EP2AGX95EF29C6N Datasheet, PDF (274/380 Pages) Altera Corporation – Device Interfaces and Integration

8–28
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
Differential Pin Placement Guidelines
Figure 8–23. Center and Corner PLLs Driving DPA-Enabled Differential I/Os in the Same Bank
Corner
PLL
Reference
CLK
DPA -enabled
Diff I/O
DPA - enabled
Diff I/O
DPA - enabled
Diff I/O
DPA - enabled
Diff I/O
DPA - enabled
Diff I/O
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
Reference
CLK
Center
PLL
Channels
driven by
Corner
PLL
One Unused
Channel for Buffer
Channels
driven by
Center
PLL
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation