EP2AGX95EF29C6N Datasheet, PDF (55/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 3: Memory Blocks in Arria II Devices
3–7
Memory Features
Figure 3–5 shows the address clock enable waveform during write cycle for M9K and
M144K blocks.
Figure 3–5. Address Clock Enable During Write Cycle Waveform for M9K and M144K Blocks
inclock
wraddress
data
wren
addressstall
latched address
(inside memory)
contents at a0
contents at a1
contents at a2
contents at a3
contents at a4
contents at a5
a0
a1
00
01
an
a0
XX
XX
a2
a3
02
03
a1
00
01
02
XX
XX
XX
XX
a4
a5
a6
04
05
06
a4
a5
03
04
05
Figure 3–6 shows the address clock enable waveform during the write cycle for
MLABs.
Figure 3–6. Address Clock Enable During Write Cycle Waveform for MLABs
inclock
wraddress
a0
a1
data
00
01
wren
addressstall
latched address
(inside memory)
an
a0
contents at a0
XX
contents at a1
XX
contents at a2
contents at a3
contents at a4
contents at a5
a2
a3
a4
a5
a6
02
03
04
05
06
a1
00
01
02
XX
XX
XX
XX
a4
a5
03
04
05
December 2011 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration