EP2AGX95EF29C6N Datasheet, PDF (206/380 Pages) Altera Corporation – Device Interfaces and Integration

7–4
Chapter 7: External Memory Interfaces in Arria II Devices
Memory Interfaces Pin Support for Arria II Devices
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For more information about pin location requirements, which pins to use as memory
clock pins, and pin connections between an Arria II device and an external memory
device, refer to Section I. Device and Pin Planning in volume 2 of the External Memory
Interface Handbook.
Memory clock pins in Arria II devices are generated with a DDIO register going to
differential output pins (refer to Figure 7–3), marked in the pin table with DIFFIN or
DIFFIO_RX prefixes (Arria II GX devices) and DIFFOUT, DIFFIO_TX, or DIFFIO_RX
prefixes (Arria II GZ devices). These pins support the differential output function and
you can use them as memory clock pins.
Figure 7–3. Memory Clock Generation for Arria II Devices (Note 1)
V_CC
System Clock
FPGA LEs I/O Elements
DQ
1
0
DQ
mem_clk (2)
mem_clk_n (2)
Notes to Figure 7–3:
(1) Global or regional clock networks are required for memory output clock generation to minimize jitter.
(2) The mem_clk[0] and mem_clk_n[0] pins for DDR3, DDR2, and DDR SDRAM interfaces use the I/O input buffer for feedback; therefore,
bidirectional I/O buffers are used for these pins. For memory interfaces with a differential DQS input, the input feedback buffer is configured as
differential input; for memory interfaces using a single-ended DQS input, the input buffer is configured as a single-ended input. Using a
single-ended input feedback buffer requires that the I/O standard’s V_REF voltage is provided to that I/O bank’s VREF pins.
Arria II devices offer differential input buffers for differential read-data strobe and
clock operations. In addition, Arria II devices also provide an independent DQS logic
block for each CQn pin for complementary read-data strobe and clock operations. In
the Arria II pin tables, the differential DQS pin pairs are denoted as DQS and DQSn
pins, and the complementary CQ signals are denoted as CQ and CQn pins. DQSn and
CQn pins are marked separately in the pin table. Each CQn pin connects to a DQS
logic block and the shifted CQn signals go to the negative-edge input registers in the
DQ IOE registers.
1 Use differential DQS signaling for DDR2 SDRAM interfaces running at 333 MHz.
DQ pins can be bidirectional signals, as in DDR3, DDR2, and DDR SDRAM, and
RLDRAM II common I/O (CIO) interfaces or unidirectional signals, as in QDR II+,
QDR II SRAM, and RLDRAM II separate I/O (SIO) devices. Connect the
unidirectional read-data signals to Arria II DQ pins and the unidirectional write-data
signals to a different DQ/DQS group than the read DQ/DQS group. The write clocks
must be assigned to the DQS/DQSn pins associated to this write DQ/DQS group. Do
not use the CQ/CQn pin-pair for write clocks.
1 Using a DQ/DQS group for the write-data signals minimizes output skew and allows
vertical migration. Arria II GX devices do not support vertical migration with
Arria II GZ devices.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
June 2011 Altera Corporation