EP2AGX95EF29C6N Datasheet, PDF (97/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 4: DSP Blocks in Arria II Devices
Arria II Operational Mode Descriptions
4–21
1 At compile time, you must select the option to use the loopback mode or the general
two-multiplier adder mode.
Figure 4–14. Loopback Mode for Half-DSP Block
zero_loopback
clock[3..0]
ena[3..0]
aclr[3..0]
signa
signb
output_round
output_saturate
overflow (1)
dataa_0[17..0]
loopback
datab_0[17..0]
+
dataa_1[17..0]
result[ ]
datab_1[17..0]
Half-DSP Block
Note to Figure 4–14:
(1) Block output for accumulator overflow and saturate overflow.
If all the inputs are full 18 bits and unsigned, the result requires 37 bits for
two-muliplier adder mode. Because the output data width in two-multiplier adder
mode is limited to 36 bits, this 37-bit output requirement is not allowed. Any other
combination that does not violate the 36-bit maximum result is permitted; for
example, two 16 × 16 signed two-multiplier adders is valid.
1 Two-multiplier adder mode supports the rounding and saturation logic unit. You can
use pipeline registers and output registers in the DSP block to pipeline the
multiplier-adder result, increasing the performance of the DSP block.
December 2010 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration