EP2AGX95EF29C6N Datasheet, PDF (35/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II Devices
2–5
Adaptive Logic Modules
Adaptive Logic Modules
The ALM is the basic building block of logic in the Arria II device architecture. Each
ALM contains a variety of LUT-based resources that can be divided between two
combinational adaptive LUTs (ALUTs) and two registers. With up to eight inputs for
the two combinational ALUTs, one ALM can implement various combinations of two
functions. This adaptability allows an ALM to be completely backward-compatible
with 4-input LUT architectures. One ALM can also implement any function with up
to 6-input and certain 7-input functions. In addition to the ALUT-based resources,
each ALM contains two programmable registers, two dedicated full adders, a carry
chain, a shared arithmetic chain, and a register chain. Through these dedicated
resources, an ALM can efficiently implement various arithmetic functions and shift
registers. Each ALM drives all types of interconnects: local, row, column, carry chain,
shared arithmetic chain, register chain, and direct link. Figure 2–5 shows a high-level
block diagram of the Arria II ALM.
Figure 2–5. High-Level Block Diagram of the Arria II ALM
shared_arith_in
carry_in
Combinational/Memory ALUT0
dataf0
datae0
dataa
datab
6-Input LUT
adder0
reg_chain_in
labclk
DQ
reg0
To general or
local routing
To general or
local routing
datac
datad
datae1
dataf1
6-Input LUT
adder1
Combinational/Memory ALUT1
shared_arith_out
carry_out
DQ
reg1
reg_chain_out
To general or
local routing
To general or
local routing
December 2010 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration