EP2AGX95EF29C6N Datasheet, PDF (110/380 Pages) Altera Corporation – Device Interfaces and Integration

5–2
Chapter 5: Clock Networks and PLLs in Arria II Devices
Clock Networks in Arria II Devices
Table 5–1 lists the clock resources available in Arria II devices.
Table 5–1. Clock Resources in Arria II Devices
Clock Resource
and Device
Number of Resources Available
Arria II GX
Arria II GZ
Source of Clock Resource
Arria II GX
Arria II GZ
Clock input pins
12
Single-ended
(6 Differential)
32
Single-ended
(16 Differential)
CLK[4..15],
DIFFCLK_[0..5]p/n pins
CLK[0..15]p
andCLK[0..15] n pins
GCLK networks
16
CLK[4..15] pins, PLL
clock outputs,
CLK[0..15]p and
16
programmable logic device CLK[0..15]n pins, PLL
(PLD)-transceiver interface clock outputs, and logic array
clocks, and logic array
RCLK networks
48
64/88 (1)
CLK[4..15] pins, PLL
clock outputs,
PLD-transceiver interface
clocks, and logic array
CLK[0..15]p and
CLK[0..15]n pins, PLL
clock outputs, and logic array
PCLK networks
84
(24 per device
quadrant) (2)
88
(22 per device
quadrant)
Dynamic phase alignment
(DPA) clock outputs,
PLD-transceiver interface
clocks, horizontal I/O pins,
and logic array
DPA clock outputs,
PLD-transceiver interface
clocks, horizontal I/O pins,
and logic array
GCLKs/RCLKs per
quadrant
28
32/38 (3)
16 GCLKs + 12 RCLKs
16 GCLKs + 16 RCLKs
16 GCLKs + 22 RCLKs
GCLKs/RCLKs per
device
64
80/104 (4)
16 GCLKs + 48 RCLKs
16 GCLKs + 64 RCLKs
16 GCLKs + 88 RCLKs
Notes to Table 5–1:
(1) There are 64 RCLKs in the EP2AGZ225 devices. There are 88 RCLKs in the EP2AGZ300 and EP2AGZ350 devices.
(2) There are 50 PCLKs in EP2AGX45 and EP2AGX65 devices, where 18 are on the left side and 32 on the right side. There are 59 PCLKs in
EP2AGX95 and EP2AGX125 device, where 27 are on the left side and 32 on the right side. There are 84 PCLKs in EP2AGX190 and EP2AGX260
devices, where 36 are on the left side and 48 on the right side.
(3) There are 32 GCLKs/RCLKs per quadrant in the EP2AGZ225 devices. There are 38 GCLKs/RCLKs per quadrant in the EP2AGZ300 and
EP2AGZ350 devices.
(4) There are 80 GCLKs/RCLKs per entire device in the EP2AGZ225 devices. There are 104 GCLKs/RCLKS per entire device in the EP2AGZ300 and
EP2AGZ350 devices.
Arria II GX devices have up to 12 dedicated single-ended clock pins or six dedicated
differential clock pins (DIFFCLK_[0..5]p and DIFFCLK_[0..5]n) that can drive either
the GCLK or RCLK networks. These clock pins are arranged on the three sides (top,
bottom, and right sides) of the Arria II GX device, as shown in Figure 5–1 on page 5–4
and Figure 5–3 on page 5–6.
Arria II GZ devices have up to 32 dedicated single-ended clock pins or 16 dedicated
differential clock pins (CLK[0..15]p and CLK[0..15]n) that can drive either the GCLK
or RCLK networks. These clock pins are arranged on the four sides of the Arria II GZ
device, as shown in Figure 5–2 on page 5–5 and Figure 5–4 on page 5–6.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation