EP2AGX95EF29C6N Datasheet, PDF (196/380 Pages) Altera Corporation – Device Interfaces and Integration

6–32
Chapter 6: I/O Features in Arria II Devices
Termination Schemes for I/O Standards
LVDS
The LVDS I/O standard is a differential high-speed, low-voltage swing, low-power,
general-purpose I/O (GPIO) interface standard. Arria II LVDS I/O standard requires
a 2.5-V V_CCIO level. The LVDS input buffer requires 2.5-V V_CCPD. LVDS requires a
100- termination resistor between the two signals at the input buffer. Arria II devices
provide an optional 100- differential termination resistor in the device with
R_D OCT.
Figure 6–15 shows the details of LVDS termination in Arria II devices. The Arria II GZ
R_D OCT is only available in the row I/O banks.
Figure 6–15. LVDS I/O Standard Termination for Arria II Devices (Note 1)
Termination
Differential Outputs
LVDS
Differential Inputs
External On-Board
Termination
50 Ω
50 Ω
100 Ω
Differential Outputs
Differential Inputs
OCT Receive
50 Ω
(True LVDS
Output)
50 Ω
OCT Receive
(Single-Ended
LVDS Output
with One-Resistor
Network,
LVDS_E_1R)
(1), (2)
Single-Ended Outputs
≤ 1 inch
50 Ω
Rp
50 Ω
External Resistor
100 Ω
Arria II OCT
Differential Inputs
100 Ω
Arria II OCT
OCT Receive
(Single-Ended
LVDS Output
with Three
Resistor
Network,
LVDS_E_3R) (1)
Single-Ended Outputs
Rs
Rp
Rs
50 Ω
50 Ω
External Resistor
Differential Inputs
100 Ω
Arria II OCT
Notes to Figure 6–15:
(1) For LVDS output with a three-resistor network, the R_S and R_P values are 120 and 170 , respectively. For LVDS output with a one-resistor network,
the R_P value is 120 
(2) LVDS_E_1R is available for Arria II GZ devices only.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2011 Altera Corporation