EP2AGX95EF29C6N Datasheet, PDF (101/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 4: DSP Blocks in Arria II Devices
Arria II Operational Mode Descriptions
4–25
Multiply Accumulate Mode
In multiply accumulate mode, the second-stage adder is configured as a 44-bit
accumulator or subtractor. The output of the DSP block is looped back to the
second-stage adder and added or subtracted with the two outputs of the first-stage
adder block according to Equation 4–3 on page 4–5.
Figure 4–18 shows the DSP block configured to operate in multiply accumulate mode.
Figure 4–18. Multiply Accumulate Mode Shown for Half-DSP Block
accum_sload
clock[3..0]
ena[3..0]
aclr[3..0]
signa
signb
output_round
output_saturate
chainout_sat_overflow (1)
dataa_0[ ]
datab_0[ ]
+
dataa_1[ ]
datab_1[ ]
dataa_2[ ]
44
+
result[ ]
datab_2[ ]
+
dataa_3[ ]
datab_3[ ]
Half-DSP Block
Note to Figure 4–18:
(1) Block output for saturation overflow of chainout.
A single DSP block can implement up to two independent 44-bit accumulators.
Use the dynamic accum_sload control signal to clear the accumulation. A logic 1
value on the accum_sload signal synchronously loads the accumulator with the
multiplier result only, and a logic 0 enables accumulation by adding or subtracting
the output of the DSP block (accumulator feedback) to the output of the multiplier
and first-stage adder.
December 2010 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration