EP2AGX95EF29C6N Datasheet, PDF (268/380 Pages) Altera Corporation – Device Interfaces and Integration

8–22
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
LVDS and DPA Clock Networks
Figure 8–18. LVDS and DPA Clock Networks in the Arria II GX Devices with Center PLLs
Corner 4
PLL
4
Quadrant
Quadrant
DPA
Clock
LVDS
Clock
8
No LVDS and DPA
clock networks on the
left side of the device
Center ₄
PLL
4
Center
PLL
Quadrant
Quadrant
DPA LVDS ₈
Clock Clock
4
Corner 4
PLL
Arria II GZ devices have left and right PLLs that feed into the differential transmitter
and receive channels through the LVDS and DPA clock network. The center left and
right PLLs can clock the transmitter and receive channels above and below them.
Figure 8–19 shows center PLL clocking in Arria II GZ devices.
Figure 8–19. LVDS/DPA Clocks in the Arria II GZ Devices with Center PLLs
4
LVDS
Clock
DPA
Clock
4
2
Center
PLL_L2
2
Center
PLL_L3
4
LVDS DPA
4 _{Clock Clock}
Quadrant
Quadrant
Quadrant
Quadrant
DPA
Clock
LVDS
Clock
4
4
Center
PLL_R2 ²
2
Center
PLL_R3
4
DPA LVDS
Clock Clock ⁴
For more information about Arria II devices PLL clocking restrictions, refer to
“Differential Pin Placement Guidelines” on page 8–27.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation