SH7750_08 Datasheet, PDF (970/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 21 High-performance User Debug Interface (H-UDI)
21.2.4 Interrupt Source Register (SDINT) (SH7750R Only)
The interrupt source register (SDINT) is a 16-bit register that can be read from and written to by
the CPU.
From the H-UDI pins, the INTREQ bit is set to 1 when a H-UDI interrupt command is set in the
SDIR register (Update-IR). While SDIR is holding a H-UDI interrupt command, the SDINT
register is connected between the TDI and TDO pins of the H-UDI, allowing it to be read as a 32-
bit register. In this case, the upper 16 bits will all be 0, and the lower 16 bits will represent SDINT.
From the CPU, only writing a 0 to the INTREQ bit is possible. While this bit holds a 1, the
interrupt requests continue to be issued, so this bit should always be cleared in the interrupt
handler.
This register is initialized in the Test-Logic-Reset state of TRST or TAP.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
—
— INTREQ
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R/W
Bits 15 to 1—Reserved: These bits are always read as 0. When writing, only 0s should be written
here.
Bit 0⎯Interrupt Request (INTREQ): Indicates whether or not an interrupt request has been
issued by an H-UDI interrupt command. From the CPU, the interrupt request can be cleared by
writing a 0 to this bit. If a 1 is written to this bit, it retains the value it had before the write
operation.
Rev.7.00 Oct. 10, 2008 Page 886 of 1074
REJ09B0366-0700