SH7750_08 Datasheet, PDF (850/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 16 Serial Communication Interface with FIFO (SCIF)
Error handling
No
ORER = 1?
Yes
Overrun error handling
No
ER = 1?
Yes
Receive error handling
1. Whether a framing error or parity error
has occurred that is to be read from
SCFRDR2 can be ascertained from
the FER and PER bits in SCFSR2.
2. When a break signal is received,
receive data is not transferred to
SCFRDR2 while the BRK flag is set.
However, note that the last data in
SCFRDR2 is H'00 (the break data in
which a framing error occurred is
stored).
No
BRK = 1?
Yes
Break handling
No
DR = 1?
Yes
Read receive data in SCFRDR2
Clear DR, ER, BRK flags
in SCFSR2,
and ORER flag in SCLSR2, to 0
End
Figure 16.10 Sample Serial Reception Flowchart (2)
Rev.7.00 Oct. 10, 2008 Page 766 of 1074
REJ09B0366-0700