SH7750_08 Datasheet, PDF (460/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Bus State Controller (BSC)
Bit 16—DMAC Burst Mode Transfer Priority Setting (DMABST) (SH7750R Only):
Specifies the priority of burst mode transfers by the DMAC. When OFF, the priority is as follows:
bus privilege released, refresh, DMAC, CPU. When ON, the bus privileges are released and
refresh operations are not performed until the end of the DMAC's burst transfer. This bit is
initialized at a power-on reset.
Bit 16: DMABST
0
1
Description
DMAC burst mode transfer priority specification OFF
DMAC burst mode transfer priority specification ON
(Initial value)
Bit 15—High Impedance Control (HIZMEM): Specifies the state of address and other signals
(A[25:0], BS, CSn, RD/WR, CE2A, CE2B) in software standby mode.
Bit 15: HIZMEM
0
1
Description
The A[25:0], BS, CSn, RD/WR, CE2A, and CE2B signals go to high-
impedance (High-Z) in standby mode and when the bus is released
(Initial value)
The A[25:0], BS, CSn, RD/WR, CE2A, and CE2B signals are driven in
standby mode. When the bus is released, they go to high-impedance.
Bit 14—High Impedance Control (HIZCNT): Specifies the state of the RAS and CAS signals in
software standby mode and when the bus is released.
Bit 14: HIZCNT
0
1
Description
The RAS, RAS2, WEn/CASn/DQMn, RD/CASS/FRAME, and RD2 signals
go to high-impedance (High-Z) in standby mode and when the bus is
released
(Initial value)
The RAS, RAS2, WEn/CASn/DQMn, RD/CASS/FRAME, and RD2 signals
are driven in standby mode and when the bus is released
Rev.7.00 Oct. 10, 2008 Page 376 of 1074
REJ09B0366-0700