SH7750_08 Datasheet, PDF (1044/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 22 Electrical Characteristics
CKIO
A25–A5
A4–A0
CSn
RD/WR
RD
D63–D0
(read)
BS
T1 TB2 TB1 TB2 TB1 TB2 TB1 T2
t_AD
t_AD
t_AD
t_CSD
t_RWD
t_{RSD tRSD}
t_RDS
t_RDH
t_BSD t_BSD
t_RDS
t_CSD
t_RWD
t_RSD
t_RDH
RDY
DACKn
(SA: IO ← memory)
DACKn
(DA)
t_DACD t_{DACD tDACD}
t_DACD
t_DACD
Legend:
IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
Figure 22.19 Burst ROM Bus Cycle (No Wait)
Rev.7.00 Oct. 10, 2008 Page 960 of 1074
REJ09B0366-0700