SH7750_08 Datasheet, PDF (316/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 8 Pipelining
1. General Pipeline
I
D
EX
• Instruction fetch
• Instruction
• Operation
decode
• Issue
• Register read
• Destination address calculation
for PC-relative branch
2. General Load/Store Pipeline
I
D
EX
• Instruction fetch
• Instruction
decode
• Issue
• Register read
• Address
calculation
NA
• Non-memory
data access
MA
• Memory
data access
3. Special Pipeline
I
D
• Instruction fetch
• Instruction
decode
• Issue
• Register read
SX
• Operation
NA
• Non-memory
data access
4. Special Load/Store Pipeline
I
D
• Instruction fetch
• Instruction
decode
• Issue
• Register read
5. Floating-Point Pipeline
I
D
• Instruction fetch • Instruction
decode
• Issue
• Register read
SX
• Address
calculation
MA
• Memory
data access
F1
F2
• Computation 1 • Computation 2
6. Floating-Point Extended Pipeline
I
D
• Instruction fetch
• Instruction
decode
• Issue
• Register read
F0
F1
• Computation 0 • Computation 1
7. FDIV/FSQRT Pipeline
F3
Computation: Takes several cycles
S
• Write-back
S
• Write-back
S
• Write-back
S
• Write-back
FS
• Computation 3
• Write-back
F2
• Computation 2
FS
• Computation 3
• Write-back
Figure 8.1 Basic Pipelines
Rev.7.00 Oct. 10, 2008 Page 232 of 1074
REJ09B0366-0700