SH7750_08 Datasheet, PDF (719/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

On-chip
peripheral
module
TMU
SCI, SCIF
Section 14 Direct Memory Access Controller (DMAC)
DMAC module
Count control
SARn
Registr control
Activation
control
DARn
DMATCRn
CHCRn
Request
priority
control
DMAOR
queclr0–7
DACK0, DACK1
DRAK0, DRAK1
Bus
interface
DREQ0, DREQ1
dmaqueclr0-7
8
SAR0, DAR0, DMATCR0,
Request CHCR0 only
DDT module
DTR command buffer
BAVL/ID2
D[63:0]
ID[1:0]
TDACK
External bus
32B data
buffer
Bus state
controller
Legend:
DMAORn: DMAC operation register
SARn: DMAC source address register
DARn: DMAC destination address register
DMATCRn: DMAC transfer count register
CHCRn: DMAC channel control register
Note: n = 0 to 7
DBREQ
DDTMODE
BAVL
DDTD
48 bits
id[2:0]
tdack
Request controller
CH0 CH1 CH2 CH3
CH4 CH5 CH6 CH7
TR DBREQ
Figure 14.53 Block Diagram of the DMAC
Rev.7.00 Oct. 10, 2008 Page 635 of 1074
REJ09B0366-0700