SH7750_08 Datasheet, PDF (807/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 15 Serial Communication Interface (SCI)
Workaround 2
Do not select settings a., b., and c. at the same time.
Multiplexer
(switches between clock
mode and SCK input)
Mode setting signal
Edge trigger FF
DQ
SH7750
MD0/SCK
B
A
CKIO
Figure 15.26 Example Countermeasure on SH7750
• Clock Timing
Make sure that the timing of the clock input to the SCK pin, including the delay from edge
trigger FF and the multiplexer in figure 15.26, conforms to that shown below.
CKIO
SCK
tSCKH tSCKS
tSCKH tSCKS
Figure 15.27 Clock Input Timing of SCK Pin
Rev.7.00 Oct. 10, 2008 Page 723 of 1074
REJ09B0366-0700