SH7750_08 Datasheet, PDF (546/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Bus State Controller (BSC)
Figure 13.24 shows the timing of the CAS-before-RAS refresh cycle.
The number of RAS assert cycles in the refresh cycle is specified by bits TRAS2–TRAS0 in
MCR. The specification of the RAS precharge time in the refresh cycle is determined by the
setting of bits TRC2–TRC0 in MCR.
CKIO
TRr1 TRr2 TRr3 TRr4 TRr5 Trc Trc Trc
A25–A0
CSn
RD/WR
RAS
CAS
D63–D0
BS
Figure 13.24 DRAM CAS-Before-RAS Refresh Cycle Timing (TRAS = 0, TRC = 1)
Rev.7.00 Oct. 10, 2008 Page 462 of 1074
REJ09B0366-0700