SH7750_08 Datasheet, PDF (1018/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 22 Electrical Characteristics
Table 22.29 Clock and Control Signal Timing (HD6417750F167 (V), HD6417750SF167 (V))
HD6417750SF167 (V), HD6417750F167 (V): V_DDQ = 3.0 to 3.6 V, V_DD = 1.8 V,
T_a = –20 to +75°C, C_L = 30 pF
Item
Symbol Min Max Unit Figure
EXTAL
clock input
frequency
PLL2
operating
1/2 divider
f
EX
operating
1/2 divider not f_EX
operating
16
56
MHz
8
28
PLL2 not 1/2 divider
f_EX
operating operating
2
56
1/2 divider not f
EX
operating
1
28
EXTAL clock input cycle time
EXTAL clock input low-level pulse width
EXTAL clock input high-level pulse width
EXTAL clock input rise time
EXTAL clock input fall time
CKIO clock PLL2 operating
output
PLL2 not operating
CKIO clock output cycle time
CKIO clock output low-level pulse width
CKIO clock output high-level pulse width
CKIO clock output rise time
CKIO clock output fall time
CKIO clock output low-level pulse width
CKIO clock output high-level pulse width
Power-on oscillation settling time
Power-on oscillation settling time/mode
settling
t_EXcyc
t_EXL
t_EXH
t_EXr
t
EXf
f_OP
f
OP
t
cyc
t
CKOL1
t_CKOH1
t_CKOr
t_CKOf
t_CKOL2
t
CKOH2
t_OSC1
t
OSCMD
18
1000 ns 22.1
3.5
—
ns 22.1
3.5
—
ns 22.1
—
4
ns 22.1
—
4
ns 22.1
25
84
MHz
1
84
MHz
12
1000 ns 22.2 (1)
1
—
ns 22.2 (1)
1
—
ns 22.2 (1)
—
3
ns 22.2 (1)
—
3
ns 22.2 (1)
3
—
ns 22.2 (2)
3
—
ns 22.2 (2)
10
—
ms 22.3, 22.5
10
—
ms 22.3, 22.5
SCK2 reset setup time
SCK2 reset hold time
MD reset setup time
MD reset hold time
t
SCK2RS
t_SCK2RH
t_MDRS
t_MDRH
20
—
20
—
3
—
20
—
ns 22.11
ns 22.3, 22.5, 22.11
t_cyc
22.12
ns 22.3, 22.5, 22.12
Rev.7.00 Oct. 10, 2008 Page 934 of 1074
REJ09B0366-0700