SH7750_08 Datasheet, PDF (831/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 16 Serial Communication Interface with FIFO (SCIF)
Bits 7 and 6—Receive FIFO Data Number Trigger (RTRG1, RTRG0): These bits are used to
set the number of receive data bytes that sets the receive data full (RDF) flag in the serial status
register (SCFSR2).
The RDF flag is set when the number of receive data bytes in SCFRDR2 is equal to or greater than
the trigger set number shown in the following table.
Bit 7: RTRG1
0
1
Bit 6: RTRG0
0
1
0
1
Receive Trigger Number
1
4
8
14
(Initial value)
Bits 5 and 4—Transmit FIFO Data Number Trigger (TTRG1, TTRG0): These bits are used
to set the number of remaining transmit data bytes that sets the transmit FIFO data register empty
(TDFE) flag in the serial status register (SCFSR2). The TDFE flag is set when the number of
transmit data bytes in SCFTDR2 is equal to or less than the trigger set number shown in the
following table.
• SH7750
Bit 5: TTRG1
Bit 4: TTRG0
Transmit Trigger Number
0
0
7 (9)
(Initial value)
1
3 (13)
1
0
1 (15)
1
0 (16)
Note: Figures in parentheses are the number of empty bytes in SCFTDR2 when the flag is set.
• SH7750S/SH7750R
Bit 5: TTRG1
Bit 4: TTRG0
Transmit Trigger Number
0
0
8 (8)
(Initial value)
1
4 (12)
1
0
2 (14)
1
1 (15)
Note: Figures in parentheses are the number of empty bytes in SCFTDR2 when the flag is set.
Rev.7.00 Oct. 10, 2008 Page 747 of 1074
REJ09B0366-0700