SH7750_08 Datasheet, PDF (541/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Bus State Controller (BSC)
CKIO
A25–A0
Tpc Tr1 Tr2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2
r
c1
c2
c3
c4
CSn
RD/WR
RAS
CAS
D63–D0
(read)
D63–D0
(write)
d1
d2
d3
d4
d1
d2
d3
d4
BS
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.22 (1) DRAM Burst Bus Cycle, RAS Down Mode Start
(Fast Page Mode, RCD = 0, AnW = 0)
Rev.7.00 Oct. 10, 2008 Page 457 of 1074
REJ09B0366-0700