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SH7750_08 Datasheet, PDF (304/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer | |||
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Section 7 Instruction Set
Table 7.5 Logic Operation Instructions
Instruction
Operation
Instruction Code
Privileged T Bit
AND Rm,Rn
Rn & Rm â Rn
0010nnnnmmmm1001 â
â
AND #imm,R0
R0 & imm â R0
11001001iiiiiiii â
â
AND.B #imm,@(R0,GBR) (R0 + GBR) & imm â (R0 + 11001101iiiiiiii â
â
GBR)
NOT Rm,Rn
~Rm â Rn
0110nnnnmmmm0111 â
â
OR Rm,Rn
Rn | Rm â Rn
0010nnnnmmmm1011 â
â
OR #imm,R0
R0 | imm â R0
11001011iiiiiiii â
â
OR.B #imm,@(R0,GBR) (R0 + GBR) | imm â (R0 + GBR)11001111iiiiiiii â
TAS.B @Rn
When (Rn) = 0, 1 â T
0100nnnn00011011 â
Otherwise, 0 â T
In both cases, 1 â MSB of (Rn)
Test result
TST Rm,Rn
Rn & Rm; when result = 0,
1âT
Otherwise, 0 â T
0010nnnnmmmm1000 â
Test result
TST #imm,R0
R0 & imm; when result = 0,
1âT
Otherwise, 0 â T
11001000iiiiiiii â
Test result
TST.B #imm,@(R0,GBR) (R0 + GBR) & imm; when result 11001100iiiiiiii â
= 0, 1 â T
Otherwise, 0 â T
Test result
XOR Rm,Rn
Rn ⧠Rm â Rn
0010nnnnmmmm1010 â
â
XOR #imm,R0
R0 ⧠imm â R0
11001010iiiiiiii â
â
XOR.B #imm,@(R0,GBR) (R0 + GBR) ⧠imm â (R0 + 11001110iiiiiiii â
â
GBR)
Rev.7.00 Oct. 10, 2008 Page 220 of 1074
REJ09B0366-0700
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