SH7750_08 Datasheet, PDF(44/1162 Page) Renesas Technology Corp – 32-Bit RISC Microcomputer

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

SH7750_08 Datasheet, PDF (44/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

◁

Item

Page

E.1 Pin States

1034

Table E.1 Pin States in

Reset, Power-Down

State, and Bus-

Released State

1035

Revision (See Manual for Details)

Signal Name

WE1/CAS1/DQM1

WE0/CAS0/DQM0

DACK1âDACK0

MD7/TXD

MD6/IOIS16

MD5/RAS2I/O

MD4/CE2BI/O

MD3/CE2AI/O

CKIO

STATUS1âSTATUS0

IRL3âIRL0

NMI

DREQ1âDREQ0

DRAK1âDRAK0

MD0/SCK

RXD

SCK2/MRESET

MD1/TXD2

MD2/RXD2

CTS2

MD8/RTS2

TCLK

TDO

TMS

TCK

TDI

TRST

CKIO2*21

I/O

O

O

O

I/O

I

I/O *1

I/O *3

I/O *2

O

O

I

I

I

O

I/O

I

I

I/O

I

I/O

I/O

I/O

O

I

I

I

I

O

Reset

(Power-On)

Master Slave

H

PZ

H

PZ

L

PI*14

PI*14

PI*14

PI*14

PI*14

L

PI*14

PI*14

PI*14

PI*14

PI*14

O

O

O

O

PI

PI

PI

PI

PI

PI

L

PI*14

L

PI*14

PI

PI

PI

PI*14

PI

PI*14

PI*14

PI*14

PI

PI

PI*14

PI*14

PI

PI

O

O

PI

PI

PI

PI

PI

PI

PI

PI

PZ*20O*9 PZ*20O*9

Reset

(Manual)

Master Slave

Bus

Hardware

Standby Released Standby

O

Z*13

Z*13O*4

Z*13O*4

Z

O

Z*13

Z*13O*4

Z*13O*4

Z

L

L

Z*11O*7

O

Z

Z*11

Z*11

Z*11K*18O*7 Z*11K*18O*7 Z

I*12

I*12

Z*12

I*12

Z

Z*13O*5 Z*13

Z*13O*4

Z*13O*4

Z

Z*13H*6 Z*13

Z*13H*6

Z*13

Z

Z*13H*6 Z*13

Z*13H*6

O*10Z*10 O*10Z*10 PZ

O

O

O

Z*13

O*10Z*10

O

Z

Z

ZO*16

I*12

I*12

I*12

I*12

I

I*12

I*12

I*12

I*12

I

I*11

I*11

Z*11

I*11

I

L

L

Z*11O*7

O

Z

I*11

I*11

Z*11K*18O*7 I*11OK*18 Z

I*11

I*11

Z*11

I*11

Z

I*11

I*11

I*11

I*11

Z

Z*11

Z*11

Z*11 K*18 Z*11 K*18 Z

O*7

O*7

I*11

I*11

Z*11

I*11

Z

I*11

I*11

Z*11K*18

I*11K*18

Z

I*11

I*11

Z*11K*18

I*11K*18

Z

I*11

I*11

K*11O*17 I*11O*17

Z

O

O

O

O

Z

PI

PI

PZ

PI

Z

PI

PI

PZ

PI

Z

PI

PI

PZ

PI

Z

PI

PI

PZ

PZ*20

PZ*20

PZ

O*9*20 O*9*20

PI

Z

PZ *20O*9 *20 Z

Signal Name

RD2*21

RD/WR2*21

CKIO2ENB

CA

ASEBRK/BRKACK

Reset

(Power-On)

I/O Master Slave

Reset

(Manual)

Master Slave

Bus

Hardware

Standby Released Standby

O

Z*20

Z*20PZ*9 Z*13*20 Z*9*13

Z*9*13 O*4 Z*9*13 O*4 Z

H*9 *20

O*9

O

Z*20

Z*20PZ*9 Z*13*20 Z*9*13

Z*9*13 H*4 Z*9*13

Z

H*9 *20

H*9

I

PI

PI

PI

PI

PI

PI

Z

I

I

I

I

I

I

I

I

I/O

PI*22O*22 PI*22O*22 PI*22O*22 PI*22O*22 PI*22O*22 PI*22O*22 Z

Legend:

I: Input (not Pulled Up)

O: Output

Z: High-impedance (not Pulled Up)

H: High-level output

L: Low-level output

K: Output state held

Rev.7.00 Oct. 10, 2008 Page xliv of lxxxiv

REJ09B0366-0700

▷