SH7750_08 Datasheet, PDF (165/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 3 Memory Management Unit (MMU)
H'E000 0000
H'E400 0000
Store queue
Reserved area
H'F000 0000
H'F100 0000
H'F200 0000
H'F300 0000
H'F400 0000
H'F500 0000
H'F600 0000
H'F700 0000
H'F800 0000
Instruction cache address array
Instruction cache data array
Instruction TLB address array
Instruction TLB data arrays 1 and 2
Operand cache address array
Operand cache data array
Unified TLB address array
Unified TLB data arrays 1 and 2
Reserved area
H'FC00 0000
Control register area
Figure 3.4 P4 Area
The area from H'E000 0000 to H'E3FF FFFF comprises addresses for accessing the store queues
(SQs). When the MMU is disabled (MMUCR.AT = 0), the SQ access right is specified by the
MMUCR.SQMD bit. For details, see section 4.7, Store Queues.
The area from H'F000 0000 to H'F0FF FFFF is used for direct access to the instruction cache
address array. For details, see section 4.5.1, IC Address Array.
The area from H'F100 0000 to H'F1FF FFFF is used for direct access to the instruction cache data
array. For details, see section 4.5.2, IC Data Array.
The area from H'F200 0000 to H'F2FF FFFF is used for direct access to the instruction TLB
address array. For details, see section 3.7.1, ITLB Address Array.
Rev.7.00 Oct. 10, 2008 Page 81 of 1074
REJ09B0366-0700