SH7750_08 Datasheet, PDF (936/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 20 User Break Controller (UBC)
20.1.2 Block Diagram
Figure 20.1 shows a block diagram of the UBC.
Access
control
Address
bus
Channel A
Access
comparator
Address
comparator
BBRA
BARA
BASRA
BAMRA
Data
bus
Channel B
Access
comparator
Address
comparator
BBRB
BARB
BASRB
BAMRB
Data
comparator
BDRB
BDMRB
Legend:
BBRA:
BARA:
BASRA:
BAMRA:
BBRB:
BARB:
BASRB:
BAMRB:
BDRB:
BDMRB:
BRCR:
Break bus cycle register A
Break address register A
Break ASID register A
Break address mask register A
Break bus cycle register B
Break address register B
Break ASID register B
Break address mask register B
Break data register B
Break data mask register B
Break control register
Control
BRCR
User break trap request
Figure 20.1 Block Diagram of User Break Controller
Rev.7.00 Oct. 10, 2008 Page 852 of 1074
REJ09B0366-0700