SH7750_08 Datasheet, PDF (548/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Bus State Controller (BSC)
CKIO
TRr1 TRr2 TRr3 TRr4
A25–A0
CSn
RD/WR
RAS
CAS
D63–D0
BS
TRr5 Trc Trc Trc
Figure 13.25 DRAM Self-Refresh Cycle Timing
Power-On Sequence: Regarding use of DRAM after powering on, it is requested that a wait time
(at least 100 μs or 200 μs) during which no access can be performed be provided, followed by at
least the prescribed number (usually 8) of dummy CAS-before-RAS refresh cycles. As the bus
state controller does not perform any special operations for a power-on reset, the necessary power-
on sequence must be carried out by the initialization program executed after a power-on reset.
Rev.7.00 Oct. 10, 2008 Page 464 of 1074
REJ09B0366-0700