SH7750_08 Datasheet, PDF (569/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Bus State Controller (BSC)
When both areas 2 and 3 are set to the synchronous DRAM, auto-refreshing of area 2 is
performed subsequent to area 3.
RTCNT value
RTCOR-1
RTCNT cleared to 0 when
RTCNT = RTCOR
H'00000000
RTCSR.CKS2–0
= 000 ≠ 000
Refresh
request
External bus
Refresh request cleared
by start of refresh cycle
Auto-refresh cycle
Figure 13.39 Auto-Refresh Operation
Time
Rev.7.00 Oct. 10, 2008 Page 485 of 1074
REJ09B0366-0700