SH7750_08 Datasheet, PDF (871/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 17 Smart Card Interface
With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to
state Z, and transfer is performed in MSB-first order. The start character data in this case is H'3F.
The parity bit is 0, corresponding to state Z, since even parity is stipulated for the smart card.
Inversion specified by the SINV bit applies only to the data bits, D7 to D0. For parity bit
inversion, the O/E bit in SCSMR1 is set to odd parity mode. (This applies to both transmission and
reception).
(Z)
A Z Z A Z Z Z A A Z (Z) State
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
(a) Direct convention (SDIR = SINV = O/E = 0)
(Z)
A Z Z A A A A A A Z (Z) State
Ds D7 D6 D5 D4 D3 D2 D1 D0 Dp
(b) Inverse convention (SDIR = SINV = O/E = 1)
Figure 17.5 Sample Start Character Waveforms
17.3.5 Clock
Only an internal clock generated by the on-chip baud rate generator can be used as the
transmit/receive clock for the smart card interface. The bit rate is set with the bit rate register
(SCBRR1) and the CKS1 and CKS0 bits in the serial mode register (SCSMR1). The equation for
calculating the bit rate is shown below. Table 17.5 shows some sample bit rates.
If clock output is selected with CKE0 set to 1, a clock with a frequency of 372 times the bit rate is
output from the SCK pin.
B
=
1488
×
Pck
2^{2n – 1}
×
(N
+
1)
×
10⁶
Where: N = Value set in SCBRR1 (0 ≤ N ≤ 255)
B = Bit rate (bits/s)
Rev.7.00 Oct. 10, 2008 Page 787 of 1074
REJ09B0366-0700