SH7750_08 Datasheet, PDF (646/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 14 Direct Memory Access Controller (DMAC)
[SH7750] An external request specification should be set for channels 1 to 3. For
channel 0, only single address mode can be set with the DTR format.
[SH7750S] An external request specification can be set for channels 0 to 3.
Bit 7—Transmit Mode (TM): Specifies the bus mode for transfer.
Bit 7: TM
0
1
Description
Cycle steal mode
Burst mode
(Initial value)
Bits 6 to 4—Transmit Size 2 to 0 (TS2–TS0): These bits specify the transfer data size. For
external memory access, the setting of these bits serves as the access size in section 13.3,
Operation. For register access, the setting of these bits is the size in which the register is accessed.
Bit 6: TS2
0
1
Bit 5: TS1
0
1
0
Bit 4: TS0
0
1
0
1
0
Description
Quadword size (64-bit) specification (Initial value)
Byte size (8-bit) specification
Word size (16-bit) specification
Longword size (32-bit) specification
32-byte block transfer specification
Bit 3—Reserved: This bit is always read as 0, and should only be written with 0.
Bit 2—Interrupt Enable (IE): When this bit is set to 1, an interrupt request (DMTE) is generated
after the number of data transfers specified in DMATCR (when TE = 1).
Bit 2: IE
0
1
Description
Interrupt request not generated after number of transfers specified in
DMATCR
(Initial value)
Interrupt request generated after number of transfers specified in DMATCR
Rev.7.00 Oct. 10, 2008 Page 562 of 1074
REJ09B0366-0700