SH7750_08 Datasheet, PDF (158/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 3 Memory Management Unit (MMU)
3.1.3 Register Configuration
The MMU registers are shown in table 3.1.
Table 3.1 MMU Registers
Name
Abbrevia-
Initial
tion
R/W Value^*1
P4
Address^*2
Area 7
Address^*2
Access
Size
Page table entry high
register
PTEH
R/W Undefined H'FF00 0000 H'1F00 0000 32
Page table entry low
register
PTEL
R/W Undefined H'FF00 0004 H'1F00 0004 32
Page table entry
assistance register
PTEA
R/W Undefined H'FF00 0034 H'1F00 0034 32
Translation table base TTB
register
R/W Undefined H'FF00 0008 H'1F00 0008 32
TLB exception address TEA
register
R/W Undefined H'FF00 000C H'1F00 000C 32
MMU control register MMUCR R/W H'0000 0000 H'FF00 0010 H'1F00 0010 32
Notes: 1. The initial value is the value after a power-on reset or manual reset.
2. This is the address when using the virtual/physical address space P4 area. When
making an access from physical address space area 7 using the TLB, the upper 3 bits
of the address are ignored.
3.1.4 Caution
Operation is not guaranteed if an area designated as a reserved area in this manual is accessed.
Rev.7.00 Oct. 10, 2008 Page 74 of 1074
REJ09B0366-0700