SH7750_08 Datasheet, PDF (340/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 8 Pipelining
Functional
Category No. Instruction
Instruc-
Execu-
Lock
tion Issue
tion
Group Rate Latency Pattern Stage Start Cycles
Double- 210
precision
floating-point
211
instructions
FNEG
FSQRT
DRn
DRn
LS
1
0
#1
— ——
FE
1
(23, 24)/ #41
F3 2
22
25
F1 21 3
F1 2
2
212 FSUB
DRm,DRn
FE
1
(7, 8)/9 #39
F1 2
6
213 FTRC
DRm,FPUL
FE
1
4/5
#38
F1 2
2
FPU system 214 LDS
Rm,FPUL
LS
1
1
control
instructions
215
LDS
Rm,FPSCR
CO
1
4
216 LDS.L
@Rm+,FPUL
CO
1
1/2
#1
— ——
#32
F1 3
3
#2
— ——
217 LDS.L
@Rm+,FPSCR CO
1
1/4
#33
F1 3
3
218 STS
FPUL,Rn
LS
1
3
#1
— ——
219 STS
FPSCR,Rn
CO
1
3
#1
— ——
220 STS.L
FPUL,@-Rn
CO
1
1/1
#2
— ——
221 STS.L
FPSCR,@-Rn
CO
1
1/1
#2
— ——
Graphics 222
acceleration
instructions
223
224
FMOV
FMOV
FMOV
DRm,XDn
XDm,DRn
XDm,XDn
LS
1
0
LS
1
0
LS
1
0
#1
— ——
#1
— ——
#1
— ——
225 FMOV @Rm,XDn
LS
1
2
#2
— ——
226 FMOV @Rm+,XDn
LS
1
1/2
#2
— ——
227 FMOV @(R0,Rm),XDn LS
1
2
#2
— ——
228 FMOV XDm,@Rn
LS
1
1
#2
— ——
229 FMOV XDm,@-Rm
LS
1
1/1
#2
— ——
230 FMOV XDm,@(R0,Rn) LS
1
1
#2
— ——
231 FIPR
FVm,FVn
FE
1
4/5
#42
F1 3
1
232 FRCHG
FE
1
1/4
#36
—
——
233 FSCHG
FE
1
1/4
#36
—
——
234 FTRV
XMTRX,FVn
FE
1
(5, 5, 6, #43
F0 2
4
7)/8
F1 3
4
Notes: 1. See table 8.1 for the instruction groups.
2. Latency “L1/L2...”: Latency corresponding to a write to each register, including
MACH/MACL/FPSCR.
Example: MOV.B @Rm+, Rn “1/2”: The latency for Rm is 1 cycle, and the latency for
Rn is 2 cycles.
3. Branch latency: Interval until the branch destination instruction is fetched
Rev.7.00 Oct. 10, 2008 Page 256 of 1074
REJ09B0366-0700