SH7750_08 Datasheet, PDF (832/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 16 Serial Communication Interface with FIFO (SCIF)
Bit 3—Modem Control Enable (MCE): Enables the CTS2 and RTS2 modem control signals.
Bit 3: MCE
Description
0
Modem signals disabled*
(Initial value)
1
Modem signals enabled
Note: * CTS2 is fixed at active-0 regardless of the input value, and RTS2 output is also fixed at
0.
Bit 2—Transmit FIFO Data Register Reset (TFRST): Invalidates the transmit data in the
transmit FIFO data register and resets it to the empty state.
Bit 2: TFRST
Description
0
Reset operation disabled*
(Initial value)
1
Reset operation enabled
Note: * A reset operation is performed in the event of a power-on reset or manual reset.
Bit 1—Receive FIFO Data Register Reset (RFRST): Invalidates the receive data in the receive
FIFO data register and resets it to the empty state.
Bit 1: RFRST
Description
0
Reset operation disabled*
(Initial value)
1
Reset operation enabled
Note: * A reset operation is performed in the event of a power-on reset or manual reset.
Bit 0—Loopback Test (LOOP): Internally connects the transmit output pin (TxD2) and receive
input pin (RxD2), and the RTS2 pin and CTS2 pin, enabling loopback testing.
Bit 0: LOOP
0
1
Description
Loopback test disabled
Loopback test enabled
(Initial value)
Rev.7.00 Oct. 10, 2008 Page 748 of 1074
REJ09B0366-0700