SH7750_08 Datasheet, PDF (318/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 8 Pipelining
10. OCBI: 1 issue cycle
I
D
EX
MA
S
MA
11. OCBP, OCBWB: 1 issue cycle
I
D
EX
MA
S
MA
MA
MA
MA
12. MOVCA.L: 1 issue cycle
I
D
EX
MA
S
MA
MA
MA
MA
MA
MA
13. TRAPA: 7 issue cycles
I
D
EX
NA
S
D
EX
NA
S
D
EX
NA
S
D
EX
NA
S
D
EX
NA
S
D
EX
NA
S
D
EX
NA
S
14. LDC to DBR/Rp_BANK/SSR/SPC/VBR, BSR: 1 issue cycle
I
D
EX
NA
S
SX
SX
15. LDC to GBR: 3 issue cycles
I
D
EX
NA
S
D
SX
D
SX
16. LDC to SR: 4 issue cycles
I
D
EX
NA
S
D
SX
D
SX
D
SX
17. LDC.L to DBR/Rp_BANK/SSR/SPC/VBR: 1 issue cycle
I
D
EX
MA
S
SX
SX
18. LDC.L to GBR: 3 issue cycles
I
D
EX
MA
S
D
SX
D
SX
Figure 8.2 Instruction Execution Patterns (cont)
Rev.7.00 Oct. 10, 2008 Page 234 of 1074
REJ09B0366-0700