SH7750_08 Datasheet, PDF (175/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 3 Memory Management Unit (MMU)
Data access to virtual address (VA)
VA is
VA is
in P4 area in P2 area
VA is
in P1 area
VA is in P0, U0,
or P3 area
On-chip I/O access
No
0
CCR.OCE?
1
0
CCR.CB?
1
VPNs match
and V = 1
Yes
No _{MMUCR.AT = 1}
Yes
CCR.WT?
0
No
1
SH = 0
and (MMUCR.SV = 0 or
SR.MD = 0)
Yes
No
VPNs match
and ASIDs match and
V=1
Yes
Data TLB miss
exception
00 or
01 W
PR?
10
R/W?
R
Data TLB protection
violation exception
Only one
No
entry matches
Yes
0 (User)
SR.MD?
1 (Privileged)
Data TLB multiple
hit exception
11
R/W? ^W
Memory access
01 or 11
00 or 10
W _R/W?
R/W? ^W
R
1
R
D?
0
R
Data TLB protection
violation exception
Initial page write
exception
Cache access
in copy-back mode
C=1
No
and CCR.OCE = 1
Yes
0
WT?
1
Cache access
in write-through mode
Memory access
(Non-cacheable)
Figure 3.10 Flowchart of Memory Access Using UTLB
Rev.7.00 Oct. 10, 2008 Page 91 of 1074
REJ09B0366-0700