SH7750_08 Datasheet, PDF (578/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Bus State Controller (BSC)
CKIO
Bank
Precharge-sel
Address
CSn
RD/WR
RAS
CASS
DQMn
Tr Trw Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Tc8 Trw1 Trw1 Tpc
Row
Row
H/L
H/L
Row
c1
c5
D31–D0 (read)
BS
CKE
DACKn
(SA: IO → memory)
c1
c2
c3
c4
c5
c6
c7
c8
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.44 Basic Timing of a Burst Write to Synchronous DRAM
Connecting a 128-Mbit/256-Mbit Synchronous DRAM with 64-bit Bus Width (SH7750R
Only): It is possible to connect 128-Mbit or 256-Mbit synchronous DRAMs with 64-bit bus width
to the SH7750R. RAS down mode is also available using a 128 Mbytes of external memory space
in area 2 or 3. Either eight 128-Mbit (4 M × 8 bit × 4 bank) DRAMs or four 256-Mbit (4 M × 8 bit
× 4 bank) DRAMs can be connected. Figure 13.45 shows an example in which four 256-Mbit
DRAMs are connected.
Notes on Usage:
• BCR1.DRAMTP2−DRAMTP0 = 011: Sets areas 2 and 3 as synchronous-DRAM-interface
spaces.
• MCR.SZ = 00: Sets the bus width of the synchronous DRAM to 64 bits.
• MCR.AMX = 6: Selects the 128-Mbit or 256-Mbit address-multiplex setting for the
synchronous DRAM.
• In the auto-refresh operation, the REF command is issued twice continuously in response to a
single refresh request. The interval cycle number between the first and second REF commands
issuance is specified by the setting of the TRAS2–TRAS0 bits in MCR, which is 4 to 11 CKIO
Rev.7.00 Oct. 10, 2008 Page 494 of 1074
REJ09B0366-0700