SH7750_08 Datasheet, PDF (813/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 16 Serial Communication Interface with FIFO (SCIF)
16.1.4 Register Configuration
The SCIF has the internal registers shown in table 16.2. These registers are used to specify the
data format and bit rate, and to perform transmitter/receiver control.
Table 16.2 SCIF Registers
Name
Abbrevia-
tion
R/W
Initial
Value
P4
Address
Area 7
Address
Access
Size
Serial mode register
SCSMR2 R/W H'0000 H'FFE80000 H'1FE80000 16
Bit rate register
SCBRR2 R/W H'FF
H'FFE80004 H'1FE80004 8
Serial control register
SCSCR2 R/W H'0000 H'FFE80008 H'1FE80008 16
Transmit FIFO data register SCFTDR2 W
Undefined H'FFE8000C H'1FE8000C 8
Serial status register
SCFSR2 R/(W)^*1 H'0060 H'FFE80010 H'1FE80010 16
Receive FIFO data register SCFRDR2 R
Undefined H'FFE80014 H'1FE80014 8
FIFO control register
SCFCR2 R/W H'0000 H'FFE80018 H'1FE80018 16
FIFO data count register
Serial port register
Line status register
SCFDR2 R
H'0000
SCSPTR2 R/W H'0000^*2
SCLSR2 R/(W)^*3 H'0000
H'FFE8001C H'1FE8001C 16
H'FFE80020 H'1FE80020 16
H'FFE80024 H'1FE80024 16
Notes: 1. Only 0 can be written, to clear flags. Bits 15 to 8, 3, and 2 are read-only, and cannot be
modified.
2. The value of bits 6, 4, and 0 is undefined.
3. Only 0 can be written, to clear flags. Bits 15 to 1 are read-only, and cannot be modified.
16.2 Register Descriptions
16.2.1 Receive Shift Register (SCRSR2)
Bit: 7
6
5
4
3
2
1
0
R/W: —
—
—
—
—
—
—
—
SCRSR2 is the register used to receive serial data.
The SCIF sets serial data input from the RxD2 pin in SCRSR2 in the order received, starting with
the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is
transferred to the receive FIFO register, SCFRDR2, automatically.
Rev.7.00 Oct. 10, 2008 Page 729 of 1074
REJ09B0366-0700