SH7750_08 Datasheet, PDF (93/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

1.2 Block Diagram
Figure 1.1 shows an internal block diagram of this LSI.
Section 1 Overview
CPU
UBC
FPU
Lower 32-bit data
Lower 32-bit data
SH-4 Core
I cache
Cache and
ITLB
TLB
UTLB
controller
O cache
CPG
INTC
SCI
(SCIF)
RTC
TMU
BSC
DMAC
External
bus interface
26-bit
address
64-bit
data
Legend:
BSC: Bus state controller
CPG: Clock pulse generator
DMAC: Direct memory access controller
FPU: Floating-point unit
INTC: Interrupt controller
ITLB: Instruction TLB (translation lookaside buffer)
UTLB:
RTC:
SCI:
SCIF:
TMU:
UBC:
Unified TLB (translation lookaside buffer)
Realtime clock
Serial communication interface
Serial communication interface with FIFO
Timer unit
User break controller
Figure 1.1 Block Diagram of SH7750/SH7750S/SH7750R Group Functions
Rev.7.00 Oct. 10, 2008 Page 9 of 1074
REJ09B0366-0700