SH7750_08 Datasheet, PDF (263/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 5 Exceptions
(2) IRL Interrupts
• Source: The interrupt mask bit setting in SR is smaller than the IRL (3–0) level, and the BL bit
in SR is 0 (accepted at instruction boundary).
• Transition address: VBR + H'0000 0600
• Transition operations:
The PC contents immediately after the instruction at which the interrupt is accepted are set in
SPC. The SR and R15 contents at the time of acceptance are set in SSR and SGR.
The code corresponding to the IRL (3–0) level is set in INTEVT. See table 19.5, Interrupt
Exception Handling Sources and Priority Order, for the corresponding codes. The BL, MD,
and RB bits are set to 1 in SR, and a branch is made to VBR + H'0600. The acceptance level is
not set in the interrupt mask bits in SR. When the BL bit in SR is 1, the interrupt is masked.
For details, see section 19, Interrupt Controller (INTC).
IRL()
{
SPC = PC;
SSR = SR;
SGR = R15;
INTEVT = H'00000200 ~ H'000003C0;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'00000600;
}
Rev.7.00 Oct. 10, 2008 Page 179 of 1074
REJ09B0366-0700