SH7750_08 Datasheet, PDF (378/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 10 Clock Oscillation Circuits
Notes: 1. The multiplication factor of PLL 1 is solely determined by the clock operating mode.
2. For the ranges of input clock frequency, see the descriptions of the EXTAL clock input
frequency (f ) and CKIO clock output (f ) in section 22.3.1, Clock and Control Signal
EX
OP
Timing.
Table 10.4 FRQCR Settings and Internal Clock Frequencies
FRQCR
(Lower 9 Bits)
Frequency Division Ratio of Frequency Divider 2
CPU Clock
Bus Clock
Peripheral Module Clock
H'008
1
1/2
1/2
H'00A
1/4
H'00C
1/8
H'011
1/3
1/3
H'013
1/6
H'01A
1/4
1/4
H'01C
1/8
H'023
1/6
1/6
H'02C
1/8
1/8
H'05A
1/2
1/4
1/4
H'05C
1/8
H'063
1/6
1/6
H'06C
1/8
1/8
H'0A3
1/3
1/6
1/6
H'0EC
1/4
1/8
1/8
Note: For the lower 9 bits of FRQCR, do not set values other than those shown in the table.
Rev.7.00 Oct. 10, 2008 Page 294 of 1074
REJ09B0366-0700